1. Field of the Invention
This invention relates to semiconductor devices and more particularly to MOSFET (Metal Oxide Semiconductor Field Effect Transistor) memory devices and methods of manufacture thereof.
2. Description of Related Art
U.S. Pat. No. 5,103,274 of Tang et al. for "Self-Aligned Source Process and Apparatus" shows a method of forming self-aligning source region EPROM, flash EPROM and EEPROM memory devices.
U.S. Pat. No. 5,120,671 of Tang et al. for "Process for Self-Aligning a Source Region with a Field Oxide Region and a Polysilicon Gate" also shows a method of forming self-aligning source region EPROM, flash EPROM and EEPROM memory devices.
See U.S. Pat. No. 5,656,513 of Wang et al. for "Nonvolatile Memory Cell Formed Using Self-Aligning Source Implant".
Also see U.S. Pat. No. 5,466,624 of Ong et al. for "Isolation Between Diffusion Lines in a Memory Array".